Conventionally, a gate driver included in a display device such as an active matrix liquid crystal display device, which gate driver serves as a scanning line drive device, has the following problem. That is, the circuit scale and production costs are large because the gate driver requires (i) in a shift register circuit, as many latch circuits as scanning lines (horizontal lines) to be driven, which latch circuits output pulses according to which the scanning lines are sequentially driven and (ii) as many level shifter circuits as the scanning lines, which level shifter circuits convert the pulses into voltage signals each having a voltage level suitable for carrying out a display on the display device.
In view of this, according to Patent Literature 1, X scanning lines are divided into groups each of which has Y scanning lines, on-voltage and off-voltage are supplied to the groups, and the groups whose scanning lines are to be driven are switched over by control means 821 and switching means 822 (refer to FIG. 22). This allows a liquid crystal display device to drive the scanning lines with use of drive outputs fewer than the scanning lines. That is, the liquid crystal display device is capable of driving the scanning lines with use of (i) the level shifter circuits fewer than the scanning lines and (ii) as many scanning line drive signal generation circuits as the level shifter circuits.
Meanwhile, a level shifter circuit includes a switch, which is for controlling conversion of a pulse into a voltage signal by switching between conductive and nonconductive states in accordance with an input signal serving as a logic signal. Generally, such a switch is constituted by an n-channel MOS (Metal Oxide Semiconductor) transistor whose gate terminal receives the input signal. Note here that, in a level shifter circuit, a voltage applied to a gate terminal of an n-channel MOS transistor, which serves as a switch, is small. Therefore, in order to achieve a desired operation speed, it is necessary to increase the width of the gate terminal (refer to Patent Literature 2).